DM74LSAN Synchronous 4-Bit Binary Counter With Asynchronous Clear. These synchronous, presettable counters feature an internal carry look-ahead for . DM74LSAN datasheet, DM74LSAN circuit, DM74LSAN data sheet: NSC – Synchronous 4-Bit Binary Counters,alldatasheet, datasheet, Datasheet. DM74LSAN datasheet, DM74LSAN circuit, DM74LSAN data sheet: FAIRCHILD – Synchronous 4-Bit Binary Counters,alldatasheet, datasheet.

Author: Yosida Nikocage
Country: El Salvador
Language: English (Spanish)
Genre: Politics
Published (Last): 7 December 2007
Pages: 111
PDF File Size: 12.61 Mb
ePub File Size: 19.15 Mb
ISBN: 693-1-20669-368-6
Downloads: 30556
Price: Free* [*Free Regsitration Required]
Uploader: Kajizuru

Typical propagation time, clock to Q output 14 ns. The device should not be operated at these limits.

DM74LSAM (Fairchild) – Synchronous 4-Bit Binary Counters | eet

The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The clear function for the DM74LSA is synchronous; and a low level at the clear inputs sets all four of the flip-flop outputs LOW after the next clock pulse, regardless of the levels of the enable inputs. The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed.

Clock Frequency Note 3. Specify by appending the suffix letter “X” to the ordering datasneet.

The function of the counter whether enabled, dis- abled, loading, or counting will be dictated solely by the conditions meeting the stable set-up and hold times. Devices also available in Tape and Reel. The gate output is connected to the daasheet input to synchronously clear the counter to all low outputs.


As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable input. Operating Free Air Temperature Datasneet. These counters feature a fully independent clock circuit.

Clear Release Time Note 3.

Fairchild Semiconductor

The input pulses are supplied by generators having the following characteristics: Vary PRR to measure f. This synchronous clear allows the count length to be modified easily, as decoding the maximum count desired can dm74ls161n accomplished with one external NAND gate. Carry output for n-bit cascading. Clear Release Time Note 2.

DM74LS161A Datasheet PDF

Free Air Operating Temperature. These counters are fully programmable; that is, the outputs may be preset to either level. This mode of operation eliminates the output counting spikes which are normally associated with asynchronous ripple clock counters.

The carry output is decoded by means of a NOR gate, thus preventing spikes during the normal counting mode of operation. These synchronous, presettable counters feature an inter- nal carry look-ahead for application in high-speed counting designs. Clock Frequency Note 2. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without addi- tional gating. The clear function for the DM74LSA is asynchro- nous; and a low level at the clear input sets all four of the flip-flop outputs LOW, regardless of the levels of clock, load, or enable inputs.


Enable P and enable T setup times are measured at t. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Search field Part name Part description. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output.

Internal look-ahead for fast counting. A buffered clock input triggers the four flip-flops on the rising positive-going edge of the clock input waveform.

d74ls161an The ripple carry output thus enabled will produce a high- level output pulse with a duration approximately equal to the high-level portion of the Q.

Typical clock frequency 32 MHz. Synchronous operation is pro- vided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating. Changes made to control inputs enable P or T or load that will modify the operating mode have no effect until clocking occurs. Typical power dissipation 93 mW.

iPhone X